Plenary Talks
Trends and perspectives for electrical characterization and reliability assessment in advanced CMOS devices and technologies
Dr. Guido Groeseneken
IMEC
With the continuous downscaling of CMOS technologies, reliability is more and more becoming a major bottleneck, and an issue of concern. When scaling down technologies below 45nm, we are reaching a situation where the power supply voltage cannot be scaled any longer because of the limitation imposed by the subthreshold slope. This means that internal electrical fields and current densities as well as power density and chip temperatures are increasing again. At the same time an impressive effort is taking place in introducing new materials and device concepts to maintain the effective performance scaling. New materials like high k dielectrics for both logic and memory technologies are being introduced, while Ge or III-V materials for high mobility devices and novel device concepts such as Multiple gate FET’s are under investigation. These new materials and devices often have unknown reliability behavior and/or introduce new failure mechanisms, whereas the speed of introduction exceeds the capabilities to explore their reliability performance in great detail.
In this paper we will discuss some of the implications these trends have on the reliability characterization and lifetime assessment of these technologies. After a brief historical review of the evolution of device reliability research, we will show how established characterization techniques, such as C-V analysis have to be revised when applied to Ge or III-V materials, whereas novel characterization techniques, such as TSCIS (Trap spectroscopy by Charge Injection and Sensing) can be introduced to help overcome the problem of dielectric material screening for logic and memory applications. Also it will be demonstrated how even single traps can cause large threshold voltage shifts in nanometer devices, in this way increasing the time-dependent variability of the device parameters. In the last part it will be shown that, when using the classical reliability assessment methodology based on accelerated testing, the available reliability margins are strongly reduced, in some cases even down to zero. As a result, the reliability community has to look more in details of what exactly is determining these margins, and how the reliability assessment methodology can be changed in order to gain new margin for the most advanced technologies. More and more reliability engineers will have to account for the impact of failures on circuit functionality to guarantee sufficient and realistic lifetimes for the products, and as a consequence more interaction with the designers will become necessary in the future.